1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more specifically, it relates to a nonvolatile semiconductor memory device for writing and erasing data in and from memory cells and reading data from the memory cells with a low power supply voltage.
2. Description of the Background Art
A flash memory, which is a kind of nonvolatile semiconductor memory device, can be fabricated at a lower cost than a dynamic random access memory (DRAM), and is recently expected as a memory device for the future generation.
FIG. 59 is a circuit diagram showing the structure of a memory cell array 5000 of a conventional NOR flash memory. A plurality of word lines WL and a plurality of bit lines BL are arranged on the memory cell array 5000. FIG. 59 representatively shows word lines WL1, WL2, WL3, . . . and bit lines BL1, BL2 and BL3, . . . Memory cells QC are provided on the respective intersections between the word lines WL and the bit lines BL. The memory cells MC are formed by floating gate MOS transistors.
The structure of a memory cell transistor forming each memory cell QC is now described.
FIG. 60 is a model sectional view for illustrating the memory cell transistor of the conventional nonvolatile semiconductor memory device. As shown in FIG. 60, the memory cell transistor has an N-type source region 2 and an N-type drain region 3 formed on a major surface of a P-type semiconductor substrate 1, a floating gate electrode 5 formed above a channel region which is held between the source region 2 and the drain region 3 through a tunnel oxide film 4, and a control gate electrode 7 formed above the floating gate electrode 5 through an insulating film 6. The source region 2 and the drain region 3 of each memory cell transistor is formed by ion implantation through masks of side wall insulating films 9 formed on side walls of the floating gate electrode 5 and the control gate electrode 7.
Referring to FIGS. 59 and 60, a source line SL is connected to the source region 2 of each memory cell QC. A bit line BL is connected to the drain region 3. A word line WL is connected to the control gate electrode 7.
The source-to-drain conductivity (channel conductance) varies with a potential applied to the control gate electrode 7. The potential of the control electrode 7, which is so increased that a current starts to flow between the source and the drain, is called a threshold voltage Vth. The threshold voltage Vth is increased as electrons are stored in the floating gate electrode 5.
The memory cell transistor stores information by changing the charged state of the floating gate electrode 5. The floating gate electrode 5, which is electrically isolated from the exterior by the insulating films 9, is in a structure for storing information in a nonvolatile manner.
Read, write and erase operations of the NOR flash memory are now briefly described.
In the write operation, electrons are injected into the floating gate 5 by channel hot electron injection. Thus, the threshold voltage Vth of the memory cell transistor changes from a low level to a high level.
In the erase operation, the electrons are extracted from the floating gate electrode 5 by an F-N (Fowler-Nordheim's) tunnel phenomenon at a gate edge of the source or the drain. Thus, the threshold voltage Vth changes from a high level to a low level.
In the read operation, a voltage of about 1 V is applied to a selected bit line BL and an external power supply voltage VCC is supplied to a selected word line WL, for reading information depending on whether or not a current flows between the source and the drain of the memory cell transistor positioned on the intersection between the selected word line WL and the selected bit line BL.
FIGS. 61 and 62 illustrate threshold voltage distributions of the NOR flash memory. As shown in FIG. 61, such a state that the threshold voltage Vth is higher than the external power supply voltage VCC (5 V) is referred to as a write state, and such a state that the threshold voltage Vth is lower than the external power supply voltage VCC (5 V) is referred to as an erase state in the NOR flash memory.
The NOR flash memory writes information bitwise, and simultaneously erases information from all bits or bits included in every prescribed block. Therefore, the threshold voltage distribution in the erase state is wider than that in the write state.
As shown in FIG. 62, employment of the present external power supply voltage VCC of 3.3 V results in the so-called overerased cells having threshold voltages Vth of not more than 1.5 V.
FIG. 63 is a circuit diagram for illustrating the problem of overerased cells in the flash memory. It is assumed that data is read from a memory cell QC1 which is connected to a bit line BL and memory cells QC2, QC3, QC4, . . . connected to the same bit line BL are overerased. A voltage of about 1 V is applied to the bit line BL, in order to read the data from the memory cell QC1. Further, the external power supply voltage VCC is applied to a word line WL1 connected with the memory cell QC1.
In this case, leakage currents i0 flow in the bit line BL through the overerased memory cells QC2, QC3, QC4, . . . although the potentials of word lines WL2, WL3, WL4, . . . connected thereto are 0 V. As a result, the selected memory cell QC1, which is in a write state, is erroneously determined as being in an erase state although no current originally flows through this memory cell QC1. Thus, the presence of such overerased cells QC2, QC3, QC4, . . . is a critical defect in operation of the flash memory.
A DINOR (divided bit line NOR) flash memory dividing bit lines into sectors is now described.
U.S. Pat. No. 5,659,505 discloses the contents of such a DINOR flash memory. The contents are now briefly described.
FIG. 64 is a circuit diagram showing the structure of a memory cell array 6000 of a conventional DINOR flash memory.
As shown in FIG. 64, the memory cell array 6000 includes two memory cell array blocks BLK0 and BLK1. FIG. 64 representatively shows four memory cell transistors MC for each memory cell array block BLK0 or BLK1. The memory cell array block BLK0 includes memory cell transistors MC1a and MC1b having drains connected to a subbit line SBL1 respectively, memory cell transistors MC2a and MC2b having drains connected to a subbit line SBL2 respectively, a selector gate SG1 opening/closing connection between a main bit line BL1 and the subbit line SBL1, and a selector gate SG2 for opening/closing connection between a main bit line BL2 and the subbit line SBL2.
Control gate electrodes of the memory cell transistors MC1a and MC2a are connected to a word line WL1, and those of the memory cell transistors MC1b and MC2b are connected to a word line WL2.
The memory cell array block BLK1 also includes memory cell transistors MC3a and MC3b having drains connected to a subbit line SBL3 respectively, and memory cell transistors MC4a and MC4b having drains connected to a subbit line SBL4 respectively.
The memory cell array block BLK1 further includes a selector gate SG3 for opening/closing connection between the main bit line BL1 and the subbit line SBL3, and a selector gate SG4 for opening/closing connection between the main bit line BL2 and the subbit line SBL4.
Control gate electrodes of the memory cell transistors MC3a and MC4a are connected to a word line WL3, and those of the memory cell transistors MC3b and MC4b are connected to a word line WL4.
The DINOR flash memory performs write, erase and read operations for memory cells after selecting the corresponding memory cell array block BLK by opening/closing the corresponding selector gate SG. Each memory cell transistor MC is formed by a floating gate MOS transistor.
The erase and write operations of the DINOR flash memory are now described.
FIG. 65 illustrates threshold voltage distributions of memory cells of the DINOR flash memory with an external. power supply voltage VCC of 3.3 V.
In the erase operation, electrons are collectively injected into the floating gate electrode 5 by an F-N tunnel phenomenon on the overall channel surface. Thus, the threshold voltage Vth changes from a low level to a high level.
In the write operation, on the other hand, the electrons are extracted by an F-N tunnel phenomenon at the gate edge of the drain. Namely, low and high threshold voltage distribution sides are referred to as write and erase states respectively in the DINOR flash memory.
Further, the DINOR flash memory extracts the electrons by applying a pulse voltage bitwise and further repeats an operation (verify operation) of verifying the threshold voltage Vth, thereby narrowing the low threshold voltage side distribution. Consequently, the lower limit of the low threshold voltage side distribution exceeds 1.5 V, to implement the operation with the external power supply voltage VCC of 3.3 V.
On the other hand, there is such a tendency that a lower voltage operation, a lower power consumption operation and a higher-speed read operation are required to a nonvolatile semiconductor memory device.
FIG. 66 illustrates threshold voltage distributions of the memory cells of the DINOR flash memory with an external power supply voltage VCC of 1.8 V.
When the external power supply voltage VC is lower than the present value of 3.3 V (e.g., 1.8 V), the lower limit of the low threshold voltage side is reduced below 1.5 V as shown in FIG. 66, to result in the so-called overwritten cells. Consequently, it is conceivably difficult to implement a read operation employing the external power supply voltage VCC as such despite the aforementioned technique of the DINOR flash memory.
In order to solve this problem, conceivable is means of stepping up the low external power supply voltage VCC to about the present voltage level (3.3 V) in read operation for applying the stepped-up voltage to word lines.
When this means is applied, however, the read operation is retarded due to the time required for the steppe operation. Further, power consumption is increased due to the steppe operation. In addition, the number of circuits operating at 3.3 V is so increased that the effect of power consumption reduction by the low voltage of 1.8 V is disadvantageously reduced.
In the DINOR memory cell structure, further, non-selected memory cells (e.g., 63 memory cells) connected to a single subbit line generate a read leakage current as a whole.
When the power supply voltage VCC is 3.3 V, the lower limit of the write threshold voltage (Vth) distribution is 1.5 V, as shown in FIG. 65. When the threshold voltage Vth is written in a value of not more than 1.5 V, the total leakage current of 63 non-selected memory cells on the same bit line to which a control gate voltage Vcg of 0 V is applied reaches a value similar to a read current Iread to disable a correct read operation, resulting in an overwrite failure.
When the threshold voltage Vth of the memory cells is 1.5 V, a current corresponding to the read current Iread flows following application of a control gate voltage Vcg of 1.5 V thereto. FIG. 67 shows current-voltage characteristics in this case.
Referring to FIG. 67, symbol Ileak denotes the value of the leakage current of the aforementioned non-selected memory cells with the control gate voltage Vcg of 0 V.
Consider a characteristic value G, expressed in the following equation, indicating inclination of the current-voltage characteristics: EQU G=.differential.(log I)/.differential.Vcg
If memory cells increasing the characteristic value G are obtained, such memory cells have the current-voltage characteristics shown by dotted lines in FIG. 67, on the assumption that the leakage current Ileak remains unchanged under the control voltage Vcg of 0 V.
If such characteristics are obtained, no overwrite failure results even if the lower limit of the write threshold voltage distribution is 0.5 V. This is because the leakage current Ileak of non-selected memory cells remains unchanged regardless of the characteristics.
If the lower limit of the write threshold voltage distribution can be reduced, reduction of a read voltage is enabled, and reduction of the power supply voltage VCC is also enabled while maintaining a high-speed read operation with no step-up.
While the physical parameters of the memory cell transistors may be changed in order to increase the characteristic value G, no remarkable improvement can be expected even in this case.
FIG. 68 shows the relation between the control gate voltage Vcg and a source-to-drain current I flowing in a memory cell transistor.
As shown in FIG. 68, the characteristic value G under the read current Iread can be remarkably increased if the value of the read current Iread can be reduced.
In general, however, reduction of the read current Iread leads to reduction of a read speed.